Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor device according to one embodiment includes a substrate, a wiring layer provided on the substrate and including source lines, a stacked body including a plurality of conductive layers and a plurality of insulating layers alternately stacked on the wiring layer, a cell film provided in the stacked body, a semiconductor film facing the cell film in the stacked body, and a diffusion film being in contact with the source lines in the wiring layer and being in contact with the semiconductor film in the stacked body. The diffusion film includes impurities and a top end portion of the diffusion film is at a higher position than a lowermost conductive layer among the conductive layers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2020-151455, filed on Sep. 9, 2020; theentire contents of which are incorporated herein by reference.

FIELD

Embodiments of the present invention relate to a semiconductor deviceand a manufacturing method thereof.

BACKGROUND

A stacked body including a plurality of electrode layers, and a channelfilm penetrating through the stacked body are provided in asemiconductor device having a memory cell array of a three-dimensionalstructure. With regard to such a structure of the semiconductor device,a DSC (Direct Strap Contact) structure is known where a sidewall of thechannel film is in direct contact with source lines provided below thestacked body. The channel film produces holes due to gate-induced drainleakage (GIDL). When sufficient holes are accumulated, data is erased.

In the semiconductor device having the DSC structure described above,the source lines are doped with impurities such as phosphorus (P). Theseimpurities diffuse into the channel film at the time of occurrence ofthe GIDL described above.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view illustrating a structure of relevant partsof a semiconductor device according to a first embodiment;

FIG. 2 is a diagram illustrating a part of a cross section along asection line A-A illustrated in FIG. 1;

FIG. 3 is a sectional view illustrating a part of FIG. 2 in an enlargedmanner;

FIG. 4A is a sectional view illustrating a process of stacking a circuitlayer and a wiring layer on a substrate;

FIG. 4B is a sectional view illustrating a process of forming a stackedbody on the wiring layer;

FIG. 4C is a sectional view illustrating a process of forming a hole;

FIG. 4D is a sectional view illustrating a process of forming a cellfilm in holes;

FIG. 4E is a sectional view illustrating a process of forming adiffusion film;

FIG. 4F is a sectional view illustrating a process of etching a part ofthe diffusion film;

FIG. 4G is a sectional view illustrating a process of forming asemiconductor film;

FIG. 4H is a sectional view illustrating a process of forming a slit;

FIG. 4I is a sectional view illustrating a process of selectivelyetching insulating layers;

FIG. 4J is a sectional view illustrating a process of forming aconductive layer and a source line;

FIG. 4K is a sectional view illustrating a process of embedding aninsulating film in holes and slits;

FIG. 5 is a sectional view of relevant parts of a semiconductor deviceaccording to a second embodiment;

FIG. 6A is a sectional view illustrating a process of forming asemiconductor film on an inner side of a cell film;

FIG. 6B is a sectional view illustrating a process of forming a firstcore insulating film on an inner side of the semiconductor film;

FIG. 6C is a sectional view illustrating a process of etching a part ofthe first core insulating film;

FIG. 6D is a sectional view illustrating a process of annealing thefirst core insulating film; and

FIG. 6E is a sectional view illustrating a process of embedding a secondcore insulating film in holes.

DETAILED DESCRIPTION

Embodiments will now be explained with reference to the accompanyingdrawings. The present invention is not limited to the embodiments.

A semiconductor device having a memory cell array of a three-dimensionalstructure is described in the following embodiments. This semiconductordevice is a NAND non-volatile semiconductor storage device that canelectrically and freely perform erase and write of data and that canretain storage contents even when power is off.

A semiconductor device according to one embodiment includes a substrate,a wiring layer provided on the substrate and including source lines, astacked body including a plurality of conductive layers and a pluralityof insulating layers alternately stacked on the wiring layer, a cellfilm provided in the stacked body, a semiconductor film facing the cellfilm in the stacked body, and a diffusion film being in contact with thesource lines in the wiring layer and being in contact with thesemiconductor film in the stacked body. The diffusion film includesimpurities and a top end portion of the diffusion film is at a higherposition than a lowermost conductive layer among the conductive layers.

First Embodiment

FIG. 1 is a perspective view illustrating a structure of relevant partsof a semiconductor device according to a first embodiment. Asemiconductor device 1 illustrated in FIG. 1 includes a substrate 10, acircuit layer 20, a wiring layer 30, a stacked body 40, and a pluralityof columnar parts 50. In the following explanations, two directionsparallel to the substrate 10 and orthogonal to each other are an Xdirection and a Y direction. A direction perpendicular to the substrate10 and orthogonal to the X direction and the Y direction is a Zdirection. The Z direction is also the stacking direction of the stackedbody 40.

The substrate 10 is, for example, a silicon substrate. The circuit layer20 is provided on the substrate 10. The circuit layer 20 includesperipheral circuits for memory cells provided in the columnar parts 50.Transistors and the like used to drive the memory cells are arranged asthe peripheral circuits. The wiring layer 30 is provided on the circuitlayer 20. The wiring layer 30 includes source lines electricallyconnected to the columnar parts 50. The stacked body 40 is provided onthe wiring layer 30.

The stacked body 40 includes an SGD 41, a cell 42, and an SGS 43. TheSGD 41 is located in an upper layer part of the stacked body 40 andincludes a plurality of drain-side selection gate electrodes. The SGS 43is located in a lower layer part of the stacked body 40 and includes aplurality of source-side selection gate electrodes. The cell 42 islocated between the SGD 41 and SGS 43 and includes a plurality of wordlines.

The columnar parts 50 are arranged in a staggered manner in the Xdirection and the Y direction. The columnar parts 50 extend in the Zdirection in the wiring layer 30 and the stacked body 40.

FIG. 2 is a diagram illustrating a part of a cross section along asection line A-A illustrated in FIG. 1. Structures of the wiring layer30, the stacked body 40, and the columnar parts 50 are explained belowwith reference to FIG. 2.

The structure of the wiring layer 30 is explained first. Source lines301 are formed in the wiring layer 30 between an insulating layer 302and an insulating layer 303. The source lines 301 are, for example,metal such as tungsten (W), polycrystalline silicon, or amorphoussilicon doped with impurities such as phosphorus. The insulating layer302 and the insulating layer 303 include, for example, silicon dioxide(SiO₂).

The structure of the stacked body 40 is explained next. As illustratedin FIG. 2, a plurality of conductive layers 401 and a plurality ofinsulating layers 402 in a flat plate form are alternately stacked inthe Z direction in the stacked body 40. Each of the conductive layers401 includes a metal film including tungsten or the like and a barriermetal film including titanium nitride (TiN) or the like. The barriermetal films are formed between the metal films and the insulating layers402. Meanwhile, the insulating layers 402 include silicon dioxide. Theconductive layers 401 are insulated and isolated by the insulatinglayers 402.

Conductive layers 401 formed in the SGD 41 among the conductive layers401 are the drain-side selection gate electrodes described above.Conductive layers 401 formed in the cell 42 are the word lines describedabove. Conductive layers 401 formed in the SGS 43 are the source-sideselection gate electrodes described above.

The structure of the columnar parts 50 is explained next. The columnarpart 50 illustrated in FIG. 2 includes a cell film 51, a semiconductorfilm 52, a core insulating film 53, and a diffusion film 54. The cellfilm 51, the semiconductor film 52, and the core insulating film 53 areformed in the stacked body 40. The diffusion film 54 is formed in thewiring layer 30 and the stacked body 40.

FIG. 3 is a sectional view illustrating a part of FIG. 2 in an enlargedmanner. As illustrated in FIG. 3, the cell film 51 is a stacked filmincluding a block dielectric film 511, a charge accumulating film 512,and a tunnel dielectric film 513. The block dielectric film 511 and thetunnel dielectric film 513 include, for example, silicon dioxide. Thecharge accumulating film 512 includes, for example, silicon nitride(SiN). A high-dielectric constant insulating film (High-k) material maybe used as materials of the block dielectric film 511, the chargeaccumulating film 512, and the tunnel dielectric film 513.

In the semiconductor device 1 according to the present embodiment,intersections between the cell film 51 and the conductive layers 401 arevertical transistors. Among the vertical transistors, intersectionsbetween the conductive layers 401 (the drain-side selection gateelectrodes) in the SDG 41 and the cell film 51 are drain-side selectiontransistors. Intersections between the conductive layers 401 (thesource-side selection gate electrodes) in the SGS 43 and the cell film51 are source-side selection transistors. Intersections between theconductive layers 401 (the word lines) in the cell 42 and the cell film51 are memory cells. The drain-side selection transistors, the memorycells, and the source-side selection transistors are connected inseries.

The semiconductor film 52 faces the tunnel dielectric film 513. Thesemiconductor film 52 includes non-doped amorphous silicon having alower phosphorus concentration than that in the diffusion film 54. Thesemiconductor film 52 is a channel film that produces holes due to GIDL.The GIDL occurs when opposite voltages are respectively applied to adrain and a gate. When sufficient holes are accumulated, chargesaccumulated in the charge accumulating film 512, that is, data iserased.

The core insulating film 53 faces the semiconductor film 52. The coreinsulating film 53 includes, for example, silicon dioxide.

Referring back to FIG. 2, the diffusion film 54 is in contact with thesource lines 301 and is also in contact with the semiconductor film 52.In the diffusion film 54, phosphorus (P) is included as impurities inamorphous silicon. The diffusion film 54 is protruded into the SGS 43.That is, the top end portion of the diffusion film 54 is at a higherposition than a lowermost conductive layer 401. The diffusion film 54may include impurities causing the conductivity type of silicon to be ann⁻ type or a p⁻ type instead of impurities, such as phosphorus, causingthe conductivity type to be an n+ type.

A manufacturing process of the semiconductor device according to thepresent embodiment is explained below with reference to FIGS. 4A to 4K.

First, as illustrated in FIG. 4A, the circuit layer 20 and a wiringlayer 30 a are successively stacked on the substrate 10. Since thecircuit layer 20 and the wiring layer 30 a can be formed by a methodgenerally used, detailed explanations thereof are omitted. In the wiringlayer 30 a, an insulating film 301 a is formed between the insulatinglayer 302 and the insulating layer 303. This insulating film 301 a is anexample of a first insulating film including silicon nitride and isreplaced with the source line 301 in a process described later.

Next, a stacked body 40 a is formed on the wiring layer 30 a asillustrated in FIG. 4B. The stacked body 40 a can be formed, forexample, by CVD (Chemical Vapor Deposition) or ALD (Atomic LayerDeposition). In the stacked body 40 a, a plurality of insulating layers401 a and the insulating layers 402 are alternately stacked in the Zdirection. The insulating layers 402 are an example of second insulatinglayers and include, for example, silicon dioxide. The insulating layers401 a are an example of first insulating layers including siliconnitride and are replaced with the conductive layers 401 in a processdescribed later.

Next, holes 60 are formed, for example, by RIE (Reactive Ion Etching) atarrangement places of the columnar parts 50 as illustrated in FIG. 4C.The holes 60 penetrate in the Z direction through the stacked body 40 aand the insulating layers 303 and the insulating film 301 a in thewiring layer 30 to end in the insulating layer 302.

Next, the cell film 51 is formed in the holes 60 as illustrated in FIG.4D. Specifically, the block dielectric film 511, the charge accumulatingfilm 512, and the tunnel dielectric film 513 illustrated in FIG. 3 areformed continuously in this order.

Next, as illustrated in FIG. 4E, the diffusion film 54 is formed on aninner side of the cell film 51, for example, by CVD. The diffusion film54 is formed using amorphous silicon doped with phosphorus. Since bottomportions of the holes 60 are narrow at that time, the bottom portionsare filled with the diffusion film 54.

Next, a part of the diffusion film 54 is etched conformally asillustrated in FIG. 4F. As a result, parts of the diffusion film 54embedded in the bottom portions of the holes 60 remain and other partsare removed. Etching of the diffusion film 54 may be dry etching such asCDE (Chemical Dry Etching) or wet etching.

In the case of dry etching, the diffusion film 54 can be etched, forexample, by introducing a mixture gas including nitrogen trifluoride(NF₃) and oxygen (O₂) under a condition of a pressure of 107 Pa (800mtorr). In the case of wet etching, the diffusion film 54 can be etched,for example, by using trimethyl-2 hydroxyethyl ammonium hydroxide (TMY)as a chemical.

Etching of the diffusion film 54 can be isotropic etching or anisotropicetching. Particularly in the case of anisotropic etching, the amount ofetching of the diffusion film 54, in other words, the height of thediffusion film 54 remaining in the bottom portions of the holes 60 canbe controlled. In the present embodiment, the top end portion of thediffusion film 54 is controlled to be at a higher position than alowermost insulating layer 401 a in the stacked body 40 a.

Next, the semiconductor film 52 is formed on an inner side of the cellfilm 51 and on the diffusion film 54 as illustrated in FIG. 4G. Thesemiconductor film 52 is, for example, a non-doped amorphous siliconfilm formed by CVD.

Subsequently, several processes are performed to form slits 61, forexample, by RIE as illustrated in FIG. 4H. The slits 61 also penetratein the Z direction through the stacked body 40 a and the insulatinglayer 303 and the insulating film 301 a in the wiring layer 30 to end inthe insulating layer 302 similarly to the holes 60.

Next, the insulating layers 401 a and the insulating films 301 a areselectively etched using the slits 61 as illustrated in FIG. 41. Forexample, a phosphoric acid solution is used as a chemical in thisetching. Parts of the cell film 51 in contact with the insulating film301 a are removed in this etching. As a result, the diffusion film 54 isexposed.

Next, as illustrated in FIG. 43, the conductive layer 401 is formed atpositions where the insulating layers 401 a have been removed and thesource line 301 is formed at positions where the insulating film 301 ahas been removed. Accordingly, the source lines 301 come in contact withthe diffusion film 54 and therefore the source lines 301 areelectrically connected to the semiconductor film 52 via the diffusionfilm 54.

Next, the core insulating film 53 is embedded in the holes 60 asillustrated in FIG. 4K. An insulating film 62 is embedded in the slits61. The insulating film 62 includes, for example, silicon dioxide.Finally, unnecessary films remaining on the top surface of the stackedbody 40 are removed. The semiconductor device 1 illustrated in FIG. 2 isthereby completed.

According to the present embodiment explained above, the diffusion film54 including phosphorus is embedded in the bottom portions of the holes60. This diffusion film 54 has a structure raised up to the SGS 43 inthe stacked body 40. Therefore, at the time of occurrence of GIDL, thediffusion distance for phosphorus is ensured and variation in thediffusion distance is reduced. This stabilizes the phosphorus diffusionrange and accordingly the data erase performance can be enhanced.

Further, formation of the diffusion film 54 eliminates the need fordoping the source lines 301 with impurities such as phosphorus in thepresent embodiment. Therefore, the source lines 301 can be formed ofmetal. In this case, a situation where silicon seams remain in thesource lines 301 can be avoided and the reliability of the device isaccordingly improved.

Second Embodiment

FIG. 5 is a sectional view of relevant parts of a semiconductor deviceaccording to a second embodiment. Constituent elements identical tothose in the first embodiment are denoted by like reference charactersand detailed explanations thereof are omitted.

A semiconductor device 2 illustrated in FIG. 5 is different from that inthe first embodiment in including a first core insulating film 53 a anda second core insulating film 53 b. The first core insulating film 53 afaces the diffusion film 54. The first core insulating film 53 aincludes the same concentration of phosphorus as that in the diffusionfilm 54 as impurities.

Meanwhile, the second core insulating film 53 b faces the semiconductorfilm 52. The phosphorus concentration in the second core insulating film53 b is lower than that in the first core insulating film 53 a.

A manufacturing process of the semiconductor device according to thepresent embodiment is explained below with reference to FIGS. 6A to 6E.Since processes until the cell film 51 is formed in the holes 60 aresame as those in the first embodiment, explanations thereof are omitted.

After the cell film 51 is formed, the semiconductor film 52 is formed onan inner side of the cell film 51, for example, by CVD as illustrated inFIG. 6A. The semiconductor film 52 is, for example, an amorphous siliconfilm.

Next, the first core insulating film 53 a is formed on an inner side ofthe semiconductor film 52, for example, by ALD as illustrated in FIG.6B. The first core insulating film 53 a is formed using silicon dioxidedoped with phosphorus. The bottom portions of the holes 60 are narrow atthat time and therefore are filled with the first core insulating film53 a.

Next, as illustrated in FIG. 6C, the first core insulating film 53 a isconformally etched. As a result, parts of the first core insulating film53 a embedded in the bottom portions of the holes 60 remain and otherparts are removed.

Etching of the first core insulating film 53 a can be dry etching suchas CDE or wet etching. Further, the etching of the first core insulatingfilm 53 a can be isotropic etching or anisotropic etching. In the caseof anisotropic etching, the amount of etching of the first coreinsulating film 53 a, in other words, the height of the first coreinsulating film 53 a remaining in the bottom portions of the holes 60can be controlled. In the present embodiment, a top end portion of thefirst core insulating film 53 a is controlled to be at a higher positionthan the lowermost insulating layer 401 a in the stacked body 40 a.

Next, the first core insulating film 53 a is annealed, for example,under a condition of a temperature higher than 1000° C. Accordingly, apart of phosphorus included in the first core insulating film 53 adiffuses into the semiconductor film 52. As a result, a part of thesemiconductor film 52 facing the first core insulating film 53 a changesto the diffusion film 54 including phosphorus as illustrated in FIG. 6D.

Next, the second core insulating film 53 b is embedded in the holes 60as illustrated in FIG. 6E. The second core insulating film 53 b includesnon-doped silicon dioxide having a lower phosphorus concentration thanthat in the first core insulating film 53 a.

Subsequently, the slits 61 (see FIG. 4J) are formed, and the insulatinglayers 401 a are replaced with the conductive layers 401 and theinsulating film 301 a is replaced with the source lines 301 using theslits 61, in the same manner as that in the first embodiment. The cellfilm 51 facing the insulating films 301 a is etched to directly connectthe source lines 301 to the diffusion film 54. The semiconductor device2 illustrated in FIG. 5 is thereby completed.

According to the embodiment explained above, the first core insulatingfilm 53 a including phosphorus is embedded in advance in the bottomportions of the holes 60. With annealing of the first core insulatingfilm 53 a, phosphorus diffuses into the semiconductor film 52 to formthe diffusion film 54. The diffusion film 54 also has a structure raisedup to the SGS 43 in the stacked body 40 similarly to the firstembodiment. Accordingly, at the time of occurrence of GIDL, thediffusion distance for phosphorus is ensured and variation in thediffusion distance is reduced. Since this stabilizes the phosphorusdiffusion range, the data erase performance can be enhanced.

Also in the present embodiment, the diffusion film 54 in contact withthe source lines 301 and the semiconductor film 52 is formed andaccordingly the need for doping the source lines 301 with impuritiessuch as phosphorus is eliminated. Therefore, with formation of thesource lines 301 with metal, a situation where silicon seams remain canbe avoided and the reliability of the device is improved.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

1. A semiconductor device comprising: a substrate; a wiring layerprovided on the substrate and including source lines; a stacked bodyincluding a plurality of conductive layers and a plurality of insulatinglayers alternately stacked on the wiring layer; a cell film provided inthe stacked body; a semiconductor film facing the cell film in thestacked body; and a diffusion film being in contact with the sourcelines in the wiring layer and being in contact with the semiconductorfilm in the stacked body, wherein the diffusion film includes impuritiesand a top end portion of the diffusion film is at a higher position thana lowermost conductive layer among the conductive layers.
 2. The deviceof claim 1, wherein the source lines include metal.
 3. The device ofclaim 1, wherein the semiconductor film is a channel film includingnon-doped silicon having a lower concentration of the impurities thanthat in the diffusion film.
 4. The device of claim 1, furthercomprising: a first core insulating film facing the diffusion film andincluding the impurities; and a second core insulating film facing thesemiconductor film on the first core insulating film and having a lowerconcentration of the impurities than that in the first core insulatingfilm.
 5. The device of claim 4, wherein a concentration of theimpurities in the first core insulating film is equal to that of theimpurities in the diffusion film.
 6. A manufacturing method of asemiconductor device, the method comprising: forming a wiring layercomprising a first insulating film on a substrate; forming a stackedbody including a plurality of first insulating layers and a plurality ofsecond insulating layers alternately stacked on the wiring layer;forming holes penetrating through the first insulating film and thestacked body; forming a cell film in the holes; embedding a diffusionfilm including impurities in bottom portions of the holes, the diffusionfilm having a top end portion at a higher position than a lowermostfirst insulating layer among the first insulating layers; forming asemiconductor film facing the cell film on the diffusion film; replacingthe first insulating film with source lines being in contact with thediffusion film; and replacing the first insulating layers withconductive layers.
 7. The method of claim 6, wherein the source line isformed of metal.
 8. The method of claim 6, wherein a channel filmincluding non-doped silicon having a lower concentration of theimpurities than that in the diffusion film is formed as thesemiconductor film.
 9. A manufacturing method of a semiconductor device,the method comprising: forming a wiring layer including a firstinsulating film on a substrate; forming a stacked body including aplurality of first insulating layers and a plurality of secondinsulating layers alternately stacked on the wiring layer; forming holespenetrating through the first insulating film and the stacked body;forming a cell film in the holes; forming a semiconductor film facingthe cell film in the holes; embedding a first core insulating filmincluding impurities in bottom portions of the holes, the first coreinsulating film having a top end portion at a higher position than alowermost first insulating layer among the first insulating layers;forming a diffusion film by diffusing the impurities from the first coreinsulating film into a part of the semiconductor film; forming a secondcore insulating film facing the semiconductor film on the first coreinsulating film; replacing the first insulating film with source linesbeing in contact with the diffusion film; and replacing the firstinsulating layers with conductive layers.
 10. The method of claim 9,wherein the source line is formed of metal.
 11. The method of claim 9,wherein a channel film including non-doped silicon having a lowerconcentration of the impurities than that in the diffusion film isformed as the semiconductor film.
 12. The method of claim 9, wherein aconcentration of the impurities in the first core insulating film isequal to that of the impurities in the diffusion film.